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MAKEFILE (at a glance)

   8:15 PM      

Sample code
 
project1: data.o main.o io.o
        cc data.o main.o io.o -o project1
data.o: data.c data.h
        cc -c data.c
main.o: data.h io.h main.c
        cc -c main.c
io.o: io.h io.c
        cc -c io.c #this is a comment

Syntex
target : source file(s)
command (must be preceded by a tab)

#command to use user defined makefile name
make -f mymakefile

Macros in make
The make program allows to use macros, which are similar to variables, to store names of files. The format is as follows:
OBJECTS = data.o io.o main.o
Whenever you want to have make expand these macros out when it runs, type the following corresponding string $(OBJECTS).

Here is sample Makefile again, using a macro.
OBJECTS = data.o main.o io.o
project1: $(OBJECTS)
        cc $(OBJECTS) -o project1
data.o: data.c data.h
        cc -c data.c
main.o: data.h io.h main.c
        cc -c main.c
io.o: io.h io.c
        cc -c io.c
You can also specify a macro's value when running make, as follows:
make 'OBJECTS=data.o newio.o main.o' project1
This overrides the value of OBJECTS in the Makefile

Special Macros
CC:
Contains the current C compiler. Defaults to cc.
CFLAGS:
Special options which are added to the built-in C rule.
$@:
Full name of the current target.
$?:
A list of files for current dependency which are out-of-date.
$<:
The source file of the current (single) dependency.

External Links:
http://www.eng.hawaii.edu/Tutor/Make/1.html
http://www.opussoftware.com/tutorial/TutMakefile.htm

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